The present invention relates to address checking in memories and more particularly to the checking of addresses to see if they fall within a given range.
In many computer operations, it is desirable to check to see if a memory address is within a specified range of such addresses. For instance, an instruction unit for certain computer systems contains an instruction buffer or I buffer that stores consecutively addressed double words fetched from a memory. When a store instruction is performed in the memory, the memory address of the store instruction must be compared to the memory addresses of the double words stored in the instruction buffer to determine if it is any of those double words that are being changed by the store operation. If it is, the buffer will be purged and all double words stored in the buffer will have to be refetched from the memory into the buffer after the store instruction has been performed. The problem with performing this comparison is that a comparison of all M plus K bits in the memory address requires expensive apparatus and incurs extensive circuit delay. On the other hand, checking only a limited number of K lower order bits of the address results in some unnecessary purging of the buffer when a check of the K lower order bits indicates a match that would be precluded if the M higher order bits were checked. In the past, the expense and circuit delay of checking a large number of bits forced the use of a relatively few number of K low order bits with the result that a significant amount of time was wasted by unnecessary purges.
Most of these schemes were involved in the performing of simultaneous selection of 2 or 3 relationships, established in a prior step, to determine if the incoming addresses were within a given range. For instance, one scheme involved checking the incoming address (ODR) with an address ICR to determine if the address ODR was inside the range of addresses spanning the address ICR through ICR plus 3 in accordance with the following formula, in which a fixed range of 4 is assumed.
INSIDE=[ICR.ltoreq.ODR&lt;(ICR plus 4)]+CARRY OUT of the incrementer for (ICR plus 4) where "+" means a logical "OR" and the word plus means an arithmetic addition. This involved performing an incrementing function (ICR plus 4) and two separate comparisons which are ANDed and then ORed to the CARRY OUT of the incrementor when there is a CARRY OUT.
Similarly, U.S. Pat. No. 3,931,611 describes a scheme using a plurality of adders each to perform a different function in determining if a range of addresses falls within a selected range.
In addition, U.S. Pat. No. 3,264,615 teaches comparing higher order address bits of a block of addresses with the corresponding bits of an address being accessed to determine if the address being accessed is in or outside of the block of addresses.
Also, U.S. Pat. No. 3,983,382 shows that in an adder of two multi-bit numbers, A and B, the condition of the sum being equal to zero can be detected by ORing the relevant product terms of bit-wise functions of the two numbers, the bit-wise functions being A.sub.i B.sub.i, A.sub.i VB.sub.i, and A.sub.i B.sub.i. The OR of such product terms can be condensed into a simplified single logic equation of such bit-wise functions.